S. F . Naz, S. Ahmed, and A. P. Shah, "QCA-based Fault-Tolerant XOR Gate for Reliable Computing with High Thermal Stability ",  Physica Scripta,  Accepted.

A. Kannaujiya, A. P. Singh, and A. P. Shah, "Noninverting Schmitt Trigger Circuit with Electronically Tunable Hysteresis ",  Microelectronics Journal,  Accepted.

S. F. Naz, D. Mondal, and A. P. Shah, "Side-Channel Attack Resilient RHBD 12T SRAM Cell for Secure Nuclear Environment",  IEEE Transactions on Device and Materials Reliability,  2023,  Accepted.

S. Shrivastava*, A. Verma*, and A. P. Shah, "BTI Resilient TG-based High-performance Ring Oscillator for PUF Design",  Analog Integrated Circuits and Signal Processing,  Vol. 116, Issue 1-2,  pp. 69-80, August 2023.

*Equal contribution

S. F. Naz,  and A. P. Shah, "Reversible Gates: A Paradigm Shift in Computing",  IEEE Open Journal of Circuits and Systems,  Vol. 4,  pp. 241 - 257, August 2023.

R. Sharma*,  D. Mondal*,  and A. P. Shah, "Radiation hardened 12T SRAM cell with improved writing capability for space applications",  Memories - Materials, Devices, Circuits and Systems,  2023,  pp. 100071, 2023

*Equal contribution

S. F. Naz,  A. P. Shah, and N. Gupta "Leakage Power Attack Resilient Schmitt Trigger Based 12T Symmetric SRAM Cell",  Microelectronics Journal,  Vol 139, September 2023,  pp. 105888.

M. Karmakar*,  S. F. Naz*,  and A. P. Shah, "Fault-Tolerant Reversible Logic Gate-based RO-PUF Design",  Memories - Materials, Devices, Circuits and Systems,  2023,  pp. 100055, 2023

*Equal contribution

A. Kannaujiya,  A. K. Patel,  S. Kannaujiya,  and A. P. Shah, "Efficient CZTSSe thin film solar cell employing MoTe2/MoS2 as hole transport layer",  Micro and Nanostructures, Vol. 169,  pp. 207356, 2022.

M. M. Fazili,  M. F. Shah,  S. F. Naz,  and A. P. Shah, "Next generation QCA technology based true random number generator for cryptographic applications",  Microelectronics Journal, Vol. 126,  pp. 105502, 2022.

M. M. Fazili,  M. F. Shah,  S. F. Naz,  and A. P. Shah, "Survey, taxonomy, and methods of QCA based design techniques–part II: reliability and security",  Semiconductor Science and Technology,  Vol. 37,  No. 6,  pp. 063002,  2022.

M. M. Fazili,  M. F. Shah,  S. F. Naz,  and A. P. Shah, "Survey,  taxonomy,  and methods of QCA based design techniques–part I: digital circuits",  Semiconductor Science and Technology,  Vol. 37,  No. 6,  pp. 063001,  2022.

N. Bhootda,  A. Yadav,  V.  Neema,  A. P.  Shah,  and S. K. Vishvakarma, "Series diode‐connected current mirror based linear and sensitive negative bias temperature instability monitoring circuit",  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields,  Vol. 35,  No. 2,  pp. e2953,  2022.

S. F. Naz,  S. Ahmed,  S. B. Ko,  A. P. Shah,  and S. Sharma, "QCA based cost efficient coplanar 1× 4 RAM design with set/reset ability",  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields,  Vol. 35,  No. 1,  pp. e2946,  2022.

A. P. Shah,  N. Gupta,  and M. Waltl, "High-performance radiation hardened NMOS only Schmitt Trigger based latch designs",  Analog Integrated Circuits and Signal Processing,  Vol. 109,  No. 3,  pp. 657-671,  2021.

P.  Raikwal,  A. P.  Shah,  and V.  Neema, "A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications",  Journal of Circuits, Systems and Computers,  Vol. 30,  No. 13,  pp. 2150243,  2021.

N. Gupta,  A. P.  Shah,  S. Khan,  S. K. Vishvakarma,  M. Waltl,  and P. Girard, "Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications",  Electronics,  Vol. 10,  No. 14,  pp. 1718,  2021.

S. Khan,  A. P. Shah,  S. S. Chouhan,  J. G. Pandey,  and S. K. Vishvakarma, "D flip-flop based TRNG with zero hardware cost for IoT security applications",  Microelectronics Reliability,  Vol. 120,  pp. 114098,  2021.

A. P. Shah,  and M. Waltl, "Impact of negative bias temperature instability on single event transients in scaled logic circuits",  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields,  Vol. 34,  No. 3,  pp. e2854,  2021.

V. Sharma,  N. Gupta,  A. P. Shah,  S. K. Vishvakarma, and S. S. Chouhan, "A reliable, multi-bit error tolerant 11T SRAM memory design for wireless sensor nodes",  Analog Integrated Circuits and Signal Processing,  Vol. 107,  No. 2,  pp. 339-352,  2021.

N. Gupta,  A. P. Shah,  R. S. Kumar,  G. Raut,  N. S. Dhakad,  and S. K. Vishvakarma, "Soft error hardened voltage bootstrapped Schmitt trigger design for reliable circuits",  Microelectronics Reliability,  Vol. 117,  pp. 114013,  2021.

N. Gupta,  A. P. Shah,  and S. K. Vishvakarma, "BTI and soft-error tolerant voltage bootstrapped Schmitt trigger circuit",  IEEE Transactions on Device and Materials Reliability,  Vol. 21,  No. 1, pp. 153-155,  2021.

N. Gupta,  V. Sharma,  A. P. Shah, S. Khan, M. Huebner,  and S. K. Vishvakarma, "An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application",  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields,  Vol. 33,  No. 6,  pp. e2766,  2020.

G. Raut,  A. P. Shah,  V. Sharma,  G. Rajput,  and S. K. Vishvakarma, "A 2.4-GS/s power-efficient, high-resolution reconfigurable dynamic comparator for ADC architecture",  Circuits, Systems, and Signal Processing,  Vol. 33,  No. 9,  pp. 4681-4694,  2020.

N. Gupta,  A. P. Shah,  R. S. Kumar,  T. Gupta,  S. Khan,  S. K. Vishvakarma, "On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell with Improved Soft Error Tolerance",  IEEE Transactions on Device and Materials Reliability,  Vol. 20,  No. 4, pp. 694-705,  2020.

S. Khan,  A. P. Shah,  S. S. Chouhan,  S. Rani,  N. Gupta,  J. G. Pandey,  and S. K. Vishvakarma, "Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications",  Analog Integrated Circuits and Signal Processing,  Vol. 103,  No. 3,  pp. 477-492,  2020.

A. P. Shah,  D. Rossi,  V. Sharma,  S. K. Vishvakarma, and M. Waltl, "Soft error hardening enhancement analysis of NBTI tolerant Schmitt trigger circuit",  Microelectronics Reliability,  Vol. 107,  pp. 113617,  2020.

A. P. Shah,  S. K. Vishvakarma, and M. M Hübner, "Soft error hardened asymmetric 10T SRAM cell for aerospace applications",  Journal of Electronic Testing,  Vol. 36, No. 2,  pp. 255-269,  2020.

S. Khan,  A. P. Shah,  S. S. Chouhan,  N. Gupta,  J. G. Pandey,  and S. K. Vishvakarma, "A symmetric D flip-flop based PUF with improved uniqueness",  Microelectronics Reliability,  Vol. 106,  pp. 113595,  2020.

A. P. Shah,  and M. Waltl, "Bias temperature instability aware and soft error tolerant radiation hardened 10T SRAM cell",  Electronics,  Vol. 9,  No. 2,  pp. 256,  2020.

A. P. Shah,  S. K. Vishvakarma,  and S. Cotofana, "NBTI stress delay sensitivity analysis of reliability enhanced Schmitt trigger based circuits",  Microelectronics Reliability,  Vol. 102,  pp. 113391,  2019.

S. Khan,  A. P. Shah,  N. Gupta,  S. S. Chouhan, J. G. Pandey,  and S. K. Vishvakarma, "An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications",  Microelectronics Journal, Vol. 92,  pp. 104605, 2019.

P. Sanvale,  N. Gupta, V. Neema,  A. P. Shah,  and S. K. Vishvakarma, "An improved read-assist energy efficient single ended PPN based 10T SRAM cell for wireless sensor network",  Microelectronics Journal, Vol. 92,  pp. 104611, 2019.

A. P. Shah,  V. Neema,  S. Daulatabad, and P. Singh, "Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits",  Microsystem Technologies, Vol. 25,  No. 5,  pp. 1639-1652, 2019.

A. P. Shah,  N. Yadav,  A. Beohar,  and S. K. Vishvakarma, "SUBHDIP: process variations tolerant subthreshold Darlington pair‐based NBTI sensor circuit",  IET Computers & Digital Techniques, Vol. 13,  No. 3,  pp. 243-249, 2019.

V. Neema,  K. Raguwanshi,  A. P. Shah,  and S. K. Vishvakarma, "Vth Extraction Based Run Time Transistor Width (TWOS) Module for On-Chip Negative Bias Temperature Instability (NBTI) Mitigation",  Sensor Letters, Vol. 17,  No. 5,  pp. 385-392, 2019.

A. P. Shah,  and S. K. Vishvakarma, “An Energy Efficient 8-Transistor Full Adder Cell Based on Degenerate Pass Transistor Logic,” IEEE VLSI Circuits & Systems Letter,  Vol. 5,  No. 2,  pp. 1-6,  2019.

N. Yadav,  A. P. Shah,  A. Beohar,  and S. K. Vishvakarma, "Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits",  Micro & Nano Letters, Vol. 14,  No. 3,  pp. 317-322, 2019.

A. Beohar,  N. Yadav,  A. P. Shah, and S. K. Vishvakarma, "Analog/RF characteristics of a 3D-Cyl underlap GAA-TFET based on a Ge source using fringing-field engineering for low-power applications",  Journal of Computational Electronics, Vol. 17,  No. 4,  pp. 1650-1657, 2018.

A. P. Shah,  N. Yadav,  A. Beohar,  and S. K. Vishvakarma, "Process variation and NBTI resilient Schmitt trigger for stable and reliable circuits",  IEEE Transactions on Device and Materials Reliability,  Vol. 18,  No. 4, pp. 546-554,  2018.

A. P. Shah,  N. Yadav,  A. Beohar,  and S. K. Vishvakarma, "An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells",  Microelectronics Reliability,  Vol. 87,  pp. 15-23,  2018.

A. P. Shah,  N. Yadav,  A. Beohar,  and S. K. Vishvakarma, "NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits",  Electronics Letters,  Vol. 54,  No. 14, pp. 868-870,  2018.

A. P. Shah,  N. Yadav,  A. Beohar,  and S. K. Vishvakarma, "On-chip adaptive body bias for reducing the impact of NBTI on 6T SRAM cells",  IEEE Transactions on Semiconductor Manufacturing,  Vol. 31,  No. 2,  pp. 242-249,  2018.

N. Yadav,  A. P. Shah,  and S. K. Vishvakarma, "Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design",  IEEE Transactions on Semiconductor Manufacturing,  Vol. 30,  No. 3,  pp. 276-284,  2017.

A. P. Shah,  R. K. Jain, and V. Neema, "A novel energy efficient high-speed 10-transistor full adder cell based on pass transistor logic",  Journal of Nanoelectronics and Optoelectronics,  Vol. 12,  No. 5,  pp. 499-504,  2017.

P. Singh, V. Neema,  S. Daulatabad, and A. P. Shah,  "Subthreshold circuit designing and implementation of finite field multiplier for cryptography application",  Procedia Computer Science,  Vol. 79,  pp. 597-602,  2016.

S. Daulatabad, V. Neema,  A. P. Shah, and P. Singh,  "8-Bit 250-MS/s ADC Based on SAR Architecture with Novel Comparator at 70 nm Technology Node",  Procedia Computer Science,  Vol. 79,  pp. 589-596,  2016.

A. P. Shah,  V. Neema, and S. Daulatabad, "DOIND: a technique for leakage reduction in nanoscale domino logic circuits",  Journal of Semiconductors,  Vol. 37,  No. 5,  pp. 055001,  2016.