A. Gupta, S. F. Naz, and  A. P.  Shah, “Configurable RO-PUF with Improved Thermal Stability for Lightweight Applications”, in 36th IEEE International Conference on Microelectronics (ICM 2024),  Doha, Qatar,  14-17 December 2024.

C. Prabhunath, and  A. P.  Shah, “Fredkin Gate-Based Feed-Forward Arbiter PUF Design on FPGA”, in 36th IEEE International Conference on Microelectronics (ICM 2024),  Doha, Qatar,  14-17 December 2024.

A. Kannaujiya, and  A. P.  Shah, “Design and Analysis of Domino Logic Schmitt Trigger Circuit for Digital Frequency Meter”, in 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2024),  Nancy, France,  18-20 November 2024.

A. Kannaujiya, V. Sahu, and  A. P.  Shah, “High-Performance Stacked Dynamic Comparator for Analog to Digital Converters”, in 28th International Symposium on VLSI Design and Test (VDAT 2024), VIT Vellore, India,  1-3 September 2024. 

🥇This paper received the Best Paper Award.

R. Khola, A. P.  Shah, and A. Shukla, “A -40◦C to 125◦C, 1.12 ppm/◦C Multiple Voltage Bandgap Reference Circuit”, in IEEE International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA 2024), Hsinchu, Taiwan, 22-25 April 2024.

A. Kannaujiya and A. P.  Shah, “NBTI Resilient Dual Mode Noise Immune Inverting Schmitt Trigger Circuit”, in 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM-2024), Bengaluru, India, 3-6 March 2024.

A. Sharma, S. F. Naz, and A. P.  Shah, “Secure and Reliable Single-Ended 10T SRAM Cell”, in 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM-2024), Bangaluru, India, 3-6 March 2024.

A. Kannaujiya and A. P.  Shah, “Robust Noise Immune Inverting Schmitt Trigger for Radiation Exposed Environment”, in 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024), Kolkata, India, 6-10 January 2024, Accepted in User Design Track.

Zainubia, B. K. Singh, M. Pundir, S. C. Dubey, and A. P.  Shah, “Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits”, in 37th International Conference on VLSI Design & the 23rd International Conference on Embedded Systems (VLSID 2024), Kolkata, India, 6-10 January 2024.

S. Singh,  A. Kannaujiya, and A. P.  Shah, “Domino Logic Based Noise Immune Schmitt Trigger Circuit”, in 9th IEEE International Symposium on Smart Electronic Systems (iSES 2023), Ahmedabad, India, 18 – 20 Dec 2023.

M. Pundir, B. K. Singh,  N. B. Kamble, and A. P.  Shah, “High-Performance Floating Resistor-based Ring Amplifier for Switched Capacitor Circuits”, in 9th IEEE Nordic Circuits and Systems Conference (NorCAS 2023), Aalborg, Denmark, October 31 - November 1, 2023.

B. K. Singh,  M. Pundir, and A. P.  Shah, “Current Mirror-based High-Performance Ring Amplifier for Switched Capacitor Circuits”, in 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2023), Istanbul, Turkey, December 4 to 7, 2023.

R. Khola, K. Kumar, N. K. Dhale, A. Kannaujiya and A. P.  Shah, “Parallel Feedback Controlled Low-Power and Reliable Schmitt Trigger Circuit,” in 27th International Symposium on VLSI Design and Test (VDAT 2023), BITS Pilani, India,  September 29 - October 01,  2023.

R. Paswan, S. Kumari, and A. P.  Shah, “An Energy Efficient Mixed Logic 2-to-4 Decoder for Embedded Memory Applications,” in 27th International Symposium on VLSI Design and Test (VDAT 2023), BITS Pilani,  India, September 29 - October 01,  2023.

S. Ahmed*,  J. Ambulkar*, D. Mondal and A. P.  Shah, “Soft Error Immune with Enhanced Critical Charge SIC14T SRAM Cell for Avionics Applications”, in 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Sharjah, UAE, October 16 - 18, 2023.

*Equal contribution

A. Kannaujiya,  U. Jangral, and A. P.  Shah, “Noninverting Schmitt Trigger Circuit with Improved Hysteresis Behavior”, in 18th Conference on PhD Research in Microelectronics and Electronics (PRIME 2023), Valencia, Spain, June 18-21, 2023.

S. F. Naz*,  M. Chawla*, and A. P.  Shah, “Leakage Power Attack and Half Select Issue Resilient Split 8T SRAM Cell”, in 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, Scotland, June 26-28, 2023.

*Equal contribution

D. Mondal*,  S. F. Naz* and A. P.  Shah, “Radiation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear Environments,” in 33rd Great Lakes Symposium on VLSI (GLSVLSI 2023),  Knoxville, TN, USA,  June 5-7,  2023.

*Equal contribution

A. Verma,  S. Srivastava and A. P.  Shah, “Aging Resilient and Energy Efficient Ring Oscillator for PUF design,” in 26th International Symposium on VLSI Design and Test (VDAT-2022), IIT Jammu,  July 17-19,  2022.

P. Sinha,  A. Sharma,  N. Naharas,  S. F. Naz and A. P.  Shah, “QCA Technology based 8-bit TRNG Design for Cryptography Applications”, in 26th International Symposium on VLSI Design and Test (VDAT-2022),  IIT Jammu,  July 17-19, 2022.

S. F. Naz, S. Khan and A. P.  Shah, “Pass Transistor XOR Gate based Radiation Hardened RO-PUF”, in 26th International Symposium on VLSI Design and Test (VDAT-2022), IIT Jammu,  July 17-19,  2022.

A. Maurya, A. Singh, S. F. Naz and A. P.  Shah, “Metastable SR Flip-Flop based True Random Number Generator using QCA Technology", in 26th International Symposium on VLSI Design and Test (VDAT-2022), IIT Jammu,  July 17-19,  2022.

M. Mythrai,  P. Pragna, Kavitha S.,  B. S. Reniwal,  P. Singh,  A. P.  Shah,  and S. K. Vishvakarma, “Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation”, in 25th International Symposium on VLSI Design and Test (VDAT-2021), SVNIT Surat, September 16-18, 2021.

N. Gupta,  N. Agrawal,  N. S. Dhakad,  A. P.  Shah,  S. K. Vishvakarma,  and P. Girard, “Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch design for Reliable Circuits”, in 31st ACM Great Lakes Symposium on VLSI (GLSVLSI’21),  USA,  June 22-25, 2021. 

S. F. Naz,  A. P.  Shah,  S. Ahmed,  P. Girard, and M. Waltl, “Design of Fault Tolerant and Thermally Stable XOR Gate in Quantum Dot Cellular Automata”, in 26th IEEE European Test Symposium 2021,  Belgium,  May 24-28, 2021.

A. P.  Shah, and P. Girard, “Impact of Aging on Soft Error Susceptibility in CMOS Circuits”, in 26th IEEE International Symposium on On-Line Testing and Robust System Design(IOLTS),  Naples, Italy,  July 13-15, 2020. 

A. Beohar,  A. P. Shah,  N. K. Yadav,  G. Raut,  and S. K. Vishvakarma, “Design and Analysis of Cyl GAA-TFET based Cross-coupled Voltage Doubler Circuit”, in 7th International Conference on Microelectronics, Circuits and Systems, New Delhi, India, July 25-26, 2020. 

N. Bhootda,  A. Yadav, V. Neema, and A. P.  Shah, “Current Mirror with Diode Connected Keeper based Linear and Sensitive NBTI Monitoring Circuits”, in 7th International Conference on Microelectronics, Circuits and Systems, New Delhi, India, July 25-26, 2020. 

🥈This paper received the Second Best Paper Award.

A. P.  Shah, and M. Waltl, “Low Cost and High Performance Radiation Hardened Latch Design for Reliable Circuits”, in 26th IEEE International Conference on Electronics Circuits and Systems,  Genova, Italy,  November 27-29, 2019,  pp. 197–200.

A. P.  Shah,  A. Moshrefi,  and M. Waltl, “Utilizing NBTI for Operation Detection of Integrated Circuits", in 23rd International Symposium on VLSI Design and Test (VDAT-2019), IIT Indore,  4-6 July 2019, pp. 190–201.

A. Beohar,  G. Raut,  G. Rajput,  A. P. Shah,  B. S. Renewal,  A. Vishvakarma, and S. K. Vishvakarma, “Compact Spiking Neural Network System with SiGe based Cylindrical Tunneling Transistor for Low Power Applications", in 23rd International Symposium on VLSI Design and Test (VDAT-2019), IIT Indore,  4-6 July 2019, pp. 655–663.

A. P.  Shah, “An Energy Efficient 8-Transistor Full Adder Cell Based on Degenerate Pass Transistor Logic”, in 33rd M.P. Young Scientist Congress, Jabalpur,  India, 15-16 March 2018,  pp. 1–10. 

A. P.  Shah,  N. Yadav,  A. Beohar, and S. K. Vishvakarma, “On-chip NBTI sensor circuits for stable and reliable CMOS circuits”, in 31st International Conference on VLSI Design, Pune, India, 6-10 January 2018, pp. 1–4. 

A. P.  Shah,  N. Yadav,  A. Beohar, and S. K. Vishvakarma, “Subthreshold darlington pair based NBTI sensor for reliable CMOS circuits”, in 13th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2017), Hsinchu, Taiwan, 18-20 October 2017,  pp. 1–2. 

A. Beohar,  A. P.  Shah,  N. Yadav,  and S. K. Vishvakarma, “Design of 3D cylindrical GAA-TFET based on germanium source with drain underlap for low power applications”, in 13th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2017), Hsinchu, Taiwan, 18-20 October 2017,  pp. 1–2. 

N. Yadav,  A. P.  Shah,  A. Beohar,  and S. K. Vishvakarma, “Source drain gaussian doping profile analysis for high ON current of InGaAs based HEMT”, in 13th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2017),  Hsinchu, Taiwan, 18-20 October 2017,  pp. 1–2. 

A. P.  Shah,  N. Yadav,  and S. K. Vishvakarma, “LISOCHIN: An NBTI degradation monitoring sensor for reliable CMOS circuits", in 21st International Symposium on VLSI Design and Test (VDAT-2017), IIT Roorkee,  June 29 – July 2, 2017,  pp. 441–451.

N. Yadav,  A. Beohar,  P. Bohra,  A. P. Shah,  and S. K. Vishvakarma, “Analytical single-trap-induced threshold voltage shift modeling for asymmetric high-k spacer FinFET”, in 4th International Conference on Production & Industrial Engineering,  Jalandhar, India, 19-21 December 2016,  pp. 1–6. 

S.  Jain,  V.  Neema,  P.  Singh,  and A. P.  Shah, “Effect of process, voltage and temperature variation in DYNOC approach for domino logic circuits", in International Conference on Smart Trends for Information Technology and Computer Communications (SmartCom 2016), Jaipur, India,  August 6–7, 2016,  pp. 831–839.

A. P.  Shah,  V. Neema, S. Daulatabad, and P. Singh, “DYNOC: an energy efficient novel approach for nanoscale domino logic circuits”, in 3rd International Conference on Microelectronics, Circuits and Systems, Kolkata,  India, July 09-10, 2016,  pp. 9–10.

A. P.  Shah, V. Neema, and S. Daulatabad, “Comparative analysis of DOIND approach with and without body biasing for leakage reduction in domino logic circuits”, in IEEE International Conference on Signal Processing, Computing and Control (ISPCC),  Waknaghat, India, 24-26 September 2015,  pp. 179–183.

A. P.  Shah, V. Neema, and S. Daulatabad, “PVT variations aware low leakage DOIND approach for nanoscale domino logic circuits”, in IEEE Power, Communication and Information Technology Conference (PCITC), Bhubaneswar, India,  15-17 October 2015,  pp. 529–534.

A. P.  Shah, V. Neema, and S. Daulatabad, “A novel leakage reduction DOIND approach for nanoscale domino logic circuits”, in IEEE Eighth International Conference on Contemporary Computing (IC3), Noida, India, 20-22 August 2015,  pp. 434–438

A. P.  Shah, V. Neema, and S. Daulatabad, “Effect of process, voltage and temperature (PVT) variations in LECTOR-B (leakage reduction technique) at 70 nm technology node”, in IEEE International Conference on Computer, Communication and Control (IC4), Indore, India, 10-12 September 2015, pp. 1–6.

A. P.  Shah, V. Neema, and S. Daulatabad, “Comparative study of area, delay and power dissipation for LECTOR and INDEP (leakage control techniques) at 70 nm technology node”, in IEEE International Advance Computing Conference (IACC), Banglore, India, 12-13 June 2015,  pp. 513–518.

A. P.  Shah, V. Neema, and S. Daulatabad, “A novel leakage reduction DOIND approach for nanoscale domino logic circuits”, in Research Scholar Congress, 23-24 May 2015, IIT Guwahati, India, pp. 1–5.